Senior Analog Layout Engineer – SerDes/PLL, 8+ yrs

A leading semiconductor company in San Jose is looking for an experienced Analog layout designer to provide onsite support. The role involves executing block and IP level Analog layout design and collaborating with global teams. Candidates should have 8+ years of experience in Analog or RF layout design and a strong grasp of debugging and layout concepts. The position offers a competitive salary ranging from $120,000 to $192,000 along with a comprehensive benefits package including bonuses, 401(k), and medical plans. #J-18808-Ljbffr