Senior Analog Layout Engineer – SerDes/PLL, 8+ yrs

A leading semiconductor company in San Jose is seeking an Analog Layout Designer to provide onsite support for advanced nodes. The ideal candidate will have over 8 years of experience in Analog or RF layout design, working on complex issues in collaboration with global teams. Responsibilities include block level design, top-level integration, and ensuring compliance with ESD and technical standards. The position offers a competitive salary range of $120,000 to $192,000, plus comprehensive benefits and the potential for bonuses. #J-18808-Ljbffr