US_East | Electrical / Electronics & Semiconductors Engineer_L4
Expedite Talent Solutions, Bloomfield, NJ, United States
Role
Principal Engineer, Design Verification
Work location: Mountain View, CA
Job Description The Principal Design Verification Engineer, within the NPU Hardware & Software organization, is intended for an individual with a broad background in design verification and complex digital system validation, with significant experience in AI accelerator verification and automotive safety standards. This role is responsible for driving the verification excellence of client’s state‑of‑the‑art Neural Processing Unit (NPU), including the development of comprehensive testbenches and validation methodologies that ensure the NPU meets the highest standards of functional correctness and performance. In addition, the role is responsible for spearheading the development of verification infrastructure, including the creation of scalable regression frameworks and coverage‑driven methodologies to deliver a high‑quality, safety‑critical NPU that meets automotive industry requirements.
Key Responsibilities
Verification Planning & Strategy (40%)
Develop comprehensive verification plans and test plans for NPU functional blocks and system‑level integration
Define verification milestones, coverage goals, and success criteria aligned with project requirements
Create verification strategies for AI‑specific workloads including convolution engines, matrix multiplication units, and activation functions
Testbench Development & Implementation (40%)
Design and implement SystemVerilog/UVM testbenches for complex NPU verification
Develop constrained random test generators for neural network inference pipelines
Create reference models and checkers for AI workload validation
Build verification environments for memory subsystems, DMA controllers, and system interconnects
Implement functional and code coverage collection and analysis methodologies
System Integration & Performance Verification (20%)
Verify AXI4/AHB protocol compliance and system‑level interfaces
Validate timing, throughput, and power consumption requirements
Develop and maintain regression test suites for continuous integration
Collaborate with software teams on hardware‑software co‑verification
Support FPGA prototyping and emulation platforms for system validation
Ensure compliance with automotive safety standards (ISO 26262) and functional safety requirements
Mandatory Skills
General Skills:
Expert communicator across global, cross‑cultural, and cross‑functional teams.
Strong analytical, debugging, and system‑level problem‑solving skills.
Proven ability to lead complex technical initiatives without direct authority.
Quality‑driven mindset with a strong focus on correctness, robustness, and coverage.
Collaborative approach across hardware, software, verification, and safety organizations.
Required Specialized Skills:
Expert SystemVerilog and UVM‑based verification
Coverage‑driven, constrained‑random, and formal verification
Verification of AI accelerators, NPUs, and complex digital subsystems
AXI4/AHB protocol and memory subsystem verification
Verification automation using Python/Perl
FPGA prototyping and emulation‑based validation
Education Required: Bachelor’s degree in Electrical Engineering or Computer Engineering.
Optional Skills
Automotive functional safety (ISO 26262)
Power‑aware and low‑power verification techniques
GenAI‑assisted verification workflows
Desired Education Master’s degree in Electrical Engineering or Computer Engineering.
#J-18808-Ljbffr
Work location: Mountain View, CA
Job Description The Principal Design Verification Engineer, within the NPU Hardware & Software organization, is intended for an individual with a broad background in design verification and complex digital system validation, with significant experience in AI accelerator verification and automotive safety standards. This role is responsible for driving the verification excellence of client’s state‑of‑the‑art Neural Processing Unit (NPU), including the development of comprehensive testbenches and validation methodologies that ensure the NPU meets the highest standards of functional correctness and performance. In addition, the role is responsible for spearheading the development of verification infrastructure, including the creation of scalable regression frameworks and coverage‑driven methodologies to deliver a high‑quality, safety‑critical NPU that meets automotive industry requirements.
Key Responsibilities
Verification Planning & Strategy (40%)
Develop comprehensive verification plans and test plans for NPU functional blocks and system‑level integration
Define verification milestones, coverage goals, and success criteria aligned with project requirements
Create verification strategies for AI‑specific workloads including convolution engines, matrix multiplication units, and activation functions
Testbench Development & Implementation (40%)
Design and implement SystemVerilog/UVM testbenches for complex NPU verification
Develop constrained random test generators for neural network inference pipelines
Create reference models and checkers for AI workload validation
Build verification environments for memory subsystems, DMA controllers, and system interconnects
Implement functional and code coverage collection and analysis methodologies
System Integration & Performance Verification (20%)
Verify AXI4/AHB protocol compliance and system‑level interfaces
Validate timing, throughput, and power consumption requirements
Develop and maintain regression test suites for continuous integration
Collaborate with software teams on hardware‑software co‑verification
Support FPGA prototyping and emulation platforms for system validation
Ensure compliance with automotive safety standards (ISO 26262) and functional safety requirements
Mandatory Skills
General Skills:
Expert communicator across global, cross‑cultural, and cross‑functional teams.
Strong analytical, debugging, and system‑level problem‑solving skills.
Proven ability to lead complex technical initiatives without direct authority.
Quality‑driven mindset with a strong focus on correctness, robustness, and coverage.
Collaborative approach across hardware, software, verification, and safety organizations.
Required Specialized Skills:
Expert SystemVerilog and UVM‑based verification
Coverage‑driven, constrained‑random, and formal verification
Verification of AI accelerators, NPUs, and complex digital subsystems
AXI4/AHB protocol and memory subsystem verification
Verification automation using Python/Perl
FPGA prototyping and emulation‑based validation
Education Required: Bachelor’s degree in Electrical Engineering or Computer Engineering.
Optional Skills
Automotive functional safety (ISO 26262)
Power‑aware and low‑power verification techniques
GenAI‑assisted verification workflows
Desired Education Master’s degree in Electrical Engineering or Computer Engineering.
#J-18808-Ljbffr