Analog Layout Engineer - FinFET & High-Speed Blocks (6mo)

A leading staffing firm is seeking an Analog Layout Engineer for a 6-month contract in San Jose, CA. This role includes layout design of Analog circuits and verification processes like DRC and LVS. Candidates should have over 5 years of experience and a degree in engineering. Proficiency with Cadence Virtuoso and a solid understanding of analog components is required. The position offers competitive pay between $90 to $110 per hour, along with various benefits including insurance and PTO. #J-18808-Ljbffr