Hybrid Lead Analog/Mixed-Signal Layout Engineer

A leading chip and silicon IP provider is seeking a Principal Layout Engineer to drive Analog/Mixed-signal product designs in San Jose, California. The role involves ownership of layouts, working with cross-functional teams, and uses advanced tools like Cadence Virtuoso. The ideal candidate will have substantial experience in CMOS layout along with familiarity with FinFET processes and a solid educational background. This full-time position offers a hybrid work environment and a competitive compensation package. #J-18808-Ljbffr