Engineering Director - Verification IP
Siemens EDA (Siemens Digital Industries Software), Austin, TX, United States
Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation!
We make real what matters.
This is your role.
* Role is based in Austin but you’ll get the chance to work with teams impacting entire cities, countries - and the shape of things to come. * Role also involves working with filed (PEs and AEs) or directly interacting with customers to deploy/resolve customer issues
We don’t need superheroes, just super minds.
* B.Tech/M.Tech in Electronics or related field from reputed institute * 15+ years of working experience in RTL design, IP/VIP development/verification or emulation experience with industry leadership. * Good level of SV, UVM Working experience. * Fair level of experience on Assertions, Coverage, Test Plan, BFM design, debug, loggers and trackers * Understanding of Register layering * Work experience on C/SystemC based tests would be an added advantage * Knowledge of one or more standard bus protocols, like PCIe/CXL, USB, Ethernet, Memory, CHI etc. * Working of coherent/non-coherent NOC would be an added advantage * Understanding various components like CPU, GPU, Display, Network, Device, Memory. * Understanding of latency, bandwidth and performance at system level.
We make real what matters.
This is your role.
* Role is based in Austin but you’ll get the chance to work with teams impacting entire cities, countries - and the shape of things to come. * Role also involves working with filed (PEs and AEs) or directly interacting with customers to deploy/resolve customer issues
We don’t need superheroes, just super minds.
* B.Tech/M.Tech in Electronics or related field from reputed institute * 15+ years of working experience in RTL design, IP/VIP development/verification or emulation experience with industry leadership. * Good level of SV, UVM Working experience. * Fair level of experience on Assertions, Coverage, Test Plan, BFM design, debug, loggers and trackers * Understanding of Register layering * Work experience on C/SystemC based tests would be an added advantage * Knowledge of one or more standard bus protocols, like PCIe/CXL, USB, Ethernet, Memory, CHI etc. * Working of coherent/non-coherent NOC would be an added advantage * Understanding various components like CPU, GPU, Display, Network, Device, Memory. * Understanding of latency, bandwidth and performance at system level.