Google
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Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA; San Diego, CA, USA .
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
4 years of experience in leading IP/SoC design teams.
Experience with Advanced RISC Machine (ARM) based SoCs, interconnects, and ASIC methodology.
Preferred qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
12 years of experience with IP design for complex IPs in Machine Learning, Neural Processors, Multimedia or GPUs.
Experience with methodologies for low power estimation, timing closure, and synthesis.
Experience managing technical teams.
Ability to drive a multi-generational roadmap for IP development.
About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full‑time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
Manage a team that delivers Machine Learning IPs for Google Silicon SoCs.
Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
Oversee Register‑Transfer Level (RTL) development, debug functional/performance simulations.
Meet schedule commitments and provide support to customers.
Participate in synthesis, timing/power estimation, and FPGA/silicon bring‑up.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Seniority level
Not Applicable
Employment type
Full‑time
Job function
Other, Information Technology, and Engineering
Industries
Information Services and Technology, Information and Internet
#J-18808-Ljbffr
Get AI-powered advice on this job and more exclusive features.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA; San Diego, CA, USA .
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
4 years of experience in leading IP/SoC design teams.
Experience with Advanced RISC Machine (ARM) based SoCs, interconnects, and ASIC methodology.
Preferred qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
12 years of experience with IP design for complex IPs in Machine Learning, Neural Processors, Multimedia or GPUs.
Experience with methodologies for low power estimation, timing closure, and synthesis.
Experience managing technical teams.
Ability to drive a multi-generational roadmap for IP development.
About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full‑time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
Manage a team that delivers Machine Learning IPs for Google Silicon SoCs.
Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
Oversee Register‑Transfer Level (RTL) development, debug functional/performance simulations.
Meet schedule commitments and provide support to customers.
Participate in synthesis, timing/power estimation, and FPGA/silicon bring‑up.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Seniority level
Not Applicable
Employment type
Full‑time
Job function
Other, Information Technology, and Engineering
Industries
Information Services and Technology, Information and Internet
#J-18808-Ljbffr