Senior Analog Layout Engineer
Capgemini Engineering, San Francisco, California, United States, 94199
Senior Analog Layout Engineer - San Jose, CA
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life‑saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities where you can make a difference and no two days are the same.
About The Role Senior layout designer responsible for the layout of high‑performance analog cores such as analog‑to‑digital converters, digital‑to‑analog converters, PLL, transceivers, etc. Lead IC layout of cutting‑edge high‑performance, high‑speed CMOS integrated circuits in foundry CMOS process nodes of 3nm, 5nm, 7nm, 16nm, following best practices from the industry.
Key Responsibilities
Thorough knowledge of industry‑standard EDA tools from Cadence, Mentor, and Synopsys.
Ability to set up LVS, DRC, and ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high‑performance analog blocks such as analog‑to‑digital converters, references, digital‑to‑analog converters, PLLs, etc.
Experience with floor planning, block‑level routing, and top‑level chip assembly.
Knowledge of high‑performance analog layout techniques, including common‑centroid layout, shielding, use of dummy devices, and thermal‑aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience working with distributed design teams.
Knowledge of SKILL code and layout automation.
Self‑starter with the ability to define and adhere to a schedule.
Strong written and verbal communication skills.
Your Profile 10+ years of experience in high‑performance analog layout in advanced CMOS process.
Experience With FinFET Process Nodes (preferred) Compensation The base compensation range for this role in the posted location is $86,900 - $203,800 / year.
Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law. The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction, including geographic location, education and qualifications, certifications and licenses, relevant experience and skills, seniority and performance, market and business consideration, and internal pay equity.
Benefits
Paid time off based on employee grade (A‑F), defined by policy: Vacation: 12‑25 days depending on grade, company‑paid holidays, personal days, sick leave.
Medical, dental, and vision coverage (or provincial healthcare coordination in Canada).
Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada).
Life and disability insurance.
Employee assistance programs.
Other benefits as provided by local policy and eligibility.
Important Notice:
Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.
Disclaimers:
Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity or expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
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About The Role Senior layout designer responsible for the layout of high‑performance analog cores such as analog‑to‑digital converters, digital‑to‑analog converters, PLL, transceivers, etc. Lead IC layout of cutting‑edge high‑performance, high‑speed CMOS integrated circuits in foundry CMOS process nodes of 3nm, 5nm, 7nm, 16nm, following best practices from the industry.
Key Responsibilities
Thorough knowledge of industry‑standard EDA tools from Cadence, Mentor, and Synopsys.
Ability to set up LVS, DRC, and ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high‑performance analog blocks such as analog‑to‑digital converters, references, digital‑to‑analog converters, PLLs, etc.
Experience with floor planning, block‑level routing, and top‑level chip assembly.
Knowledge of high‑performance analog layout techniques, including common‑centroid layout, shielding, use of dummy devices, and thermal‑aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience working with distributed design teams.
Knowledge of SKILL code and layout automation.
Self‑starter with the ability to define and adhere to a schedule.
Strong written and verbal communication skills.
Your Profile 10+ years of experience in high‑performance analog layout in advanced CMOS process.
Experience With FinFET Process Nodes (preferred) Compensation The base compensation range for this role in the posted location is $86,900 - $203,800 / year.
Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law. The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction, including geographic location, education and qualifications, certifications and licenses, relevant experience and skills, seniority and performance, market and business consideration, and internal pay equity.
Benefits
Paid time off based on employee grade (A‑F), defined by policy: Vacation: 12‑25 days depending on grade, company‑paid holidays, personal days, sick leave.
Medical, dental, and vision coverage (or provincial healthcare coordination in Canada).
Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada).
Life and disability insurance.
Employee assistance programs.
Other benefits as provided by local policy and eligibility.
Important Notice:
Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.
Disclaimers:
Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity or expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
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