Analog Layout Engineer
Axiom Global Technologies, Sunnyvale, California, United States, 94087
We are looking for a
Senior Analog Layout Engineer
to lead the physical design and layout of high-performance, high-speed CMOS integrated circuits. This role involves driving
full-custom IC layout
in advanced foundry technologies ( 3nm, 5nm, 7nm, and 16nm ) while following industry best practices to achieve optimal performance, reliability, and manufacturability.
Key Responsibilities
Lead
full-custom layout
of high-performance, high-speed analog and mixed-signal CMOS circuits.
Design and implement layouts for advanced technology nodes ( 3nm, 5nm, 7nm, 16nm ) in leading foundry processes.
Apply advanced layout techniques including
device matching, common-centroid, interdigitation, symmetry, shielding, and guard rings .
Optimize layouts for
performance, area, power, signal integrity, and yield .
Perform and resolve
DRC, LVS, ERC, and antenna violations
using industry-standard verification tools.
Conduct
parasitic extraction (PEX)
and support post-layout simulation and timing/performance closure.
Address
layout-dependent effects (LDE), EM/IR, reliability, and variation
challenges in advanced nodes.
Collaborate closely with circuit designers, verification teams, and process engineers to meet design specifications.
Drive layout reviews, enforce
industry best practices , and support
tape-out activities .
Mentor junior layout engineers and contribute to layout methodologies and design guidelines.
Required Qualifications
Bachelor’s or Master’s degree in
Electrical/Electronics Engineering
or related field.
6+ years of experience in
analog/mixed-signal full-custom layout .
Proven experience working in
advanced CMOS nodes (16nm and below) .
Strong hands-on experience with:
Calibre / Pegasus / Assura
for physical verification
Deep understanding of:
Analog layout techniques and matching strategies
High-speed layout considerations and signal integrity
Parasitic effects, LDE, and process variations
#J-18808-Ljbffr
Senior Analog Layout Engineer
to lead the physical design and layout of high-performance, high-speed CMOS integrated circuits. This role involves driving
full-custom IC layout
in advanced foundry technologies ( 3nm, 5nm, 7nm, and 16nm ) while following industry best practices to achieve optimal performance, reliability, and manufacturability.
Key Responsibilities
Lead
full-custom layout
of high-performance, high-speed analog and mixed-signal CMOS circuits.
Design and implement layouts for advanced technology nodes ( 3nm, 5nm, 7nm, 16nm ) in leading foundry processes.
Apply advanced layout techniques including
device matching, common-centroid, interdigitation, symmetry, shielding, and guard rings .
Optimize layouts for
performance, area, power, signal integrity, and yield .
Perform and resolve
DRC, LVS, ERC, and antenna violations
using industry-standard verification tools.
Conduct
parasitic extraction (PEX)
and support post-layout simulation and timing/performance closure.
Address
layout-dependent effects (LDE), EM/IR, reliability, and variation
challenges in advanced nodes.
Collaborate closely with circuit designers, verification teams, and process engineers to meet design specifications.
Drive layout reviews, enforce
industry best practices , and support
tape-out activities .
Mentor junior layout engineers and contribute to layout methodologies and design guidelines.
Required Qualifications
Bachelor’s or Master’s degree in
Electrical/Electronics Engineering
or related field.
6+ years of experience in
analog/mixed-signal full-custom layout .
Proven experience working in
advanced CMOS nodes (16nm and below) .
Strong hands-on experience with:
Calibre / Pegasus / Assura
for physical verification
Deep understanding of:
Analog layout techniques and matching strategies
High-speed layout considerations and signal integrity
Parasitic effects, LDE, and process variations
#J-18808-Ljbffr