Senior Analog Layout Engineer – 3nm/5nm/7nm ICs

A leading tech firm in Sunnyvale is searching for a Senior Analog Layout Engineer. The successful candidate will lead the layout of high-performance CMOS circuits and work with advanced technology nodes like 3nm and 5nm. Responsibilities include optimizing layouts for various performance metrics and conducting verification tasks. A requirement of 6+ years experience in the field and a degree in Electrical/Electronics Engineering is mandatory. Mentorship of junior engineers is also expected. #J-18808-Ljbffr