Senior Analog Layout Engineer — High‑Perf CMOS ICs

A leading engineering services firm is seeking a Senior Analog Layout Engineer in San Francisco. This role involves designing high-performance analog cores and leading layout projects for advanced CMOS processes. Ideal candidates have over 10 years of hands-on experience with EDA tools, strong leadership skills, and the ability to work with distributed teams. Competitive compensation is offered within the range of $86,900 - $203,800 per year, along with a comprehensive benefits package. #J-18808-Ljbffr