Analog Layout Engineer – High-Speed ICs (6-Month Contract)

A leading engineering firm in San Jose, CA is looking for an experienced Analog Layout Engineer. This role requires a minimum of 5 years in analog layout with expertise in Cadence Virtuoso and Mentor Calibre. Responsibilities include layout design for high-speed transceiver circuit blocks and conducting design verification processes. The ideal candidate holds an associate degree or higher and possesses strong communication skills. The position offers a pay rate of $90-$100 per hour for a duration of 6 months, and encourages diverse candidates to apply. #J-18808-Ljbffr