Senior Analog Layout Engineer: High-Speed IC Blocks

A leading engineering firm in San Jose is seeking an experienced Analog Layout Engineer to handle the layout of high-speed circuit blocks and components. The ideal candidate should have over 5 years of experience in analog layout within deep sub-micron processes. Proficiency in Cadence Virtuoso and Mentor Calibre is required, along with strong communication skills. As part of a collaborative team, you will ensure quality and integrity in circuit design and layout, working closely with design engineers. #J-18808-Ljbffr