Senior Analog Layout Designer – RF, SerDes & PLL

A leading semiconductor company in California is seeking an Analog Layout Designer to provide onsite support for advanced nodes. The ideal candidate will possess at least 8 years of experience in Analog or RF layout, demonstrating strong skills in debugging DRC and LVS errors. Proficiency with Cadence tools and a Bachelor's degree are required. This role offers a competitive salary ranging from $108,000 to $172,800, along with comprehensive benefits including medical and retirement plans. #J-18808-Ljbffr