Senior Analog Layout Engineer: Deep Submicron CMOS

A technology company based in San Jose, California is seeking an experienced Analog Layout Engineer. This role involves designing and implementing analog and mixed-signal layout designs for integrated circuits. Candidates should possess a B.S. in Electrical Engineering and at least 8 years of relevant experience. Proficiency in Cadence Virtuoso, Calibre DRC, and LVS is essential. Strong communication and leadership skills are required to collaborate effectively with the design team and meet project goals. #J-18808-Ljbffr