Senior Analog & RF IC Layout Engineer (FinFET 7nm)

A leading global technology company is seeking a Senior Analog / RF IC Layout Engineer in San Francisco, California. The successful candidate will design high-speed mixed-signal silicon and collaborate closely with world-class teams. Responsibilities include leading the layout of complex integrated circuits, ensuring layout quality, and mentoring junior engineers. This role offers competitive compensation ranging from $88,800 to $187,740 annually, plus a comprehensive benefits package. #J-18808-Ljbffr