Senior Analog IC Layout Engineer — High-Performance CMOS

A leading engineering services company is seeking a Senior Analog Layout Engineer in San Francisco, CA. The role requires leading the IC layout of advanced high-performance analog cores such as ADCs and PLLs, utilizing best practices and industry-standard EDA tools. Candidates should have over 10 years of experience in analog layout and strong communication skills. The role offers a competitive salary range and a comprehensive benefits package. #J-18808-Ljbffr