Senior Layout Engineer
Arm, Austin, TX, United States
About The Role
The Solutions Engineering Group is seeking a highly skilled Senior Layout Engineer to develop innovative custom standard cells targeting advanced semiconductor process technologies. You will collaborate closely with circuit designers and physical design teams to produce high‑quality layouts that meet aggressive performance, power, and area targets, drive physical implementation excellence, and influence methodologies for leading‑edge process nodes.
Responsibilities
Create, optimize, and verify custom digital standard cell layouts, realizing advanced IP in the latest process technologies.
Work within the Solutions Engineering Group on custom cell development and customer‑specific design solutions.
Collaborate with circuit design and implementation teams to ensure performance, usability, reliability, and alignment with PDK constraints.
Develop and/or aid in layout methodologies, automation scripts, and standard processes to improve productivity and consistency.
Conduct full physical verification including DRC, LVS, ERC, and resolve verification issues.
Drive continuous improvement in cell architecture, design rules understanding, and layout quality for next‑generation processes.
Required Skills And Experience
Associate’s degree in Electrical Engineering, Microelectronics, or related field, or equivalent experience.
5+ years of hands‑on mask/layout design experience in semiconductor or ASIC development.
Expert proficiency with Cadence Virtuoso and advanced layout techniques.
Experience building or enhancing standard cell libraries or high‑performance custom circuits.
Familiarity with EM/IR, reliability constraints, and design‑for‑manufacturability (DFM) practices.
Strong understanding of semiconductor device physics, PDK constraints, and layout‑dependent effects (LDE).
Proven experience performing DRC, LVS and handling signoff‑quality verification flows, interpreting reports and debugging.
Experience designing in advanced nodes (5nm and below).
Ability to interpret schematics, floorplans, and design constraints and translate them into optimized layouts.
Strategic planning and layout development for maximum reuse across multiple architectures.
Excellent communication and cross‑team collaboration skills.
Nice to Have Skills and Experience
Familiarity with scripting for layout automation (e.g., SKILL, Tcl, Python).
Background working directly with process engineering teams or supporting early‑node technology enablement.
Additional EDA tool knowledge such as Calibre, Assura, Pegasus, or similar.
Salary Range $136,400 - $184,600 per year
Accommodations If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. All requests will be treated with confidentiality and shared only as necessary.
Hybrid Working Hybrid working is designed to support high performance and personal wellbeing. Teams determine their own hybrid patterns, and details will be shared upon application.
Equal Opportunities Arm is an equal opportunity employer committed to a respectful environment where equal opportunities are available to all applicants and colleagues. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.
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Responsibilities
Create, optimize, and verify custom digital standard cell layouts, realizing advanced IP in the latest process technologies.
Work within the Solutions Engineering Group on custom cell development and customer‑specific design solutions.
Collaborate with circuit design and implementation teams to ensure performance, usability, reliability, and alignment with PDK constraints.
Develop and/or aid in layout methodologies, automation scripts, and standard processes to improve productivity and consistency.
Conduct full physical verification including DRC, LVS, ERC, and resolve verification issues.
Drive continuous improvement in cell architecture, design rules understanding, and layout quality for next‑generation processes.
Required Skills And Experience
Associate’s degree in Electrical Engineering, Microelectronics, or related field, or equivalent experience.
5+ years of hands‑on mask/layout design experience in semiconductor or ASIC development.
Expert proficiency with Cadence Virtuoso and advanced layout techniques.
Experience building or enhancing standard cell libraries or high‑performance custom circuits.
Familiarity with EM/IR, reliability constraints, and design‑for‑manufacturability (DFM) practices.
Strong understanding of semiconductor device physics, PDK constraints, and layout‑dependent effects (LDE).
Proven experience performing DRC, LVS and handling signoff‑quality verification flows, interpreting reports and debugging.
Experience designing in advanced nodes (5nm and below).
Ability to interpret schematics, floorplans, and design constraints and translate them into optimized layouts.
Strategic planning and layout development for maximum reuse across multiple architectures.
Excellent communication and cross‑team collaboration skills.
Nice to Have Skills and Experience
Familiarity with scripting for layout automation (e.g., SKILL, Tcl, Python).
Background working directly with process engineering teams or supporting early‑node technology enablement.
Additional EDA tool knowledge such as Calibre, Assura, Pegasus, or similar.
Salary Range $136,400 - $184,600 per year
Accommodations If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. All requests will be treated with confidentiality and shared only as necessary.
Hybrid Working Hybrid working is designed to support high performance and personal wellbeing. Teams determine their own hybrid patterns, and details will be shared upon application.
Equal Opportunities Arm is an equal opportunity employer committed to a respectful environment where equal opportunities are available to all applicants and colleagues. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.
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