Lead Analog Layout Engineer - Mixed-Signal ASICs

A leading technology firm in Silicon Valley is seeking an experienced Analog Layout Engineer to design and implement cutting-edge analog and mixed-signal layouts for integrated circuits. The successful candidate will lead a team while collaborating with project managers and design engineers to meet strict project goals. With a solid background in deep submicron CMOS circuits and expertise in tools like Cadence Virtuoso, you'll be instrumental in delivering high-quality designs. The position offers a competitive salary range of $110,000 to $300,000 annually. #J-18808-Ljbffr