Optical Engineer III - Design Analysis
Spectraforce Technologies, Redmond, WA, United States
Job Description Optical Engineer, Photonic Integrated Circuit (PIC) Design & Analysis
Duration: 24 Months
Location: Onsite in Redmond /WA
Responsibilities
Design and develop complete Photonic Integrated Circuits (PICs), from fundamental component blocks to full-circuit implementations, with a strong emphasis on active device integration.
Generate, verify, and prepare fabrication-ready layout files, ensuring compliance with foundry PDks (Process Design Kits) for external fabrication.
Conduct systematic design analysis, including optimization and parametric studies, to guide design decisions.
Support the entire design-to-fabrication pipeline, from initial concept through tapeout, coordinating closely with cross-functional teams and external partners.
Collaborate with program leadership, Technical Program Managers (TPMs), and researchers on PIC designs that align with overall program objectives.
Must-Have Skills
PIC Design & Simulation: 3+ years designing, simulating, and laying out photonic integrated circuits (PICs) for visible/IR wavelengths.
Photonic Modeling Tools: Proficiency with tools like Lumerical, Ansys Photonics, Synopsys RSoft, or COMSOL for device/circuit analysis.
PIC Layout & Tapeout: Experience with layout tools (KLayout, Cadence Virtuoso, gdsfactory), GDSII generation, and supporting tapeouts at commercial foundries.
Nice-to-Have Skills
Active PIC Design & Validation: Experience in active PIC design, fabrication, and validation, especially for visible wavelengths.
Device Characterization: Skills in optical/electro-optic measurements, fiber optics, free-space optics, and PIC packaging.
Statistical Modeling & Sensitivity Analysis: Experience in design space exploration, yield modeling, and incorporating fabrication constraints.
Minimum Qualifications
MS or Ph.D. degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
3+ years of hands-on experience in the design, simulation, and layout of PICs for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.
3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).
2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.
2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.
1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).
Preferred Qualifications
3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.
3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.
3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).
2+ years of experience utilizing photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.
2+ years of experience in photonic device characterization and test, including both optical and electro-optic measurements.
1+ years experience with fiber optics, free-space optics, PIC packaging, and comprehensive device characterization.
1+ years experience with semiconductor fabrication processes and a deep understanding of process-induced performance limitations, such as optical losses, sidewall roughness, and process variability.
Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementing effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).
Minimum Years of Experience
5-7
Degrees/Certifications
Required: MS or Ph.D. degree (preferred) in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
Key Projects / Day-to-Day Responsibilities
Design, simulate, and optimize PICs and photonic devices.
Prepare fabrication-ready layouts and ensure compliance with foundry PDKs.
Analyze and improve designs through parametric studies.
Coordinate the design-to-fabrication pipeline with cross-functional teams and external partners. Collaborate with leadership and researchers to align designs with program goals.
Purpose / Size of This Team & Role
Key technical contributor in the R&D team, collaborating with leadership, TPMs, and researchers. Drives PIC design and fabrication efforts, bridging technical and program objectives.
Projects / Products
Developing advanced photonic integrated circuits for next-gen near-to-eye display systems. Integrating active devices and optimizing for fabrication constraints. Improving system-level performance and yield through design analysis and modeling.
About the Team
R&D team focused on cutting-edge near-to-eye display systems. Multidisciplinary collaboration with engineers, researchers, and program managers. Drives innovation in integrated photonics and display technology.
Progress Metrics
Successful design and tapeout of PICs.
Quality and innovation in device simulation, layout, and fabrication.
Effective collaboration and alignment with program goals.
Ability to optimize designs for performance and manufacturability.
Challenges & How to Address Them
Overcoming challenges like optical losses, process variability, and device packaging.
Why This Role Appeals
Opportunity to work on cutting-edge photonics for next-generation display technology.
Collaborate with top experts in a highly innovative R&D environment.
Direct impact on product development and technology advancement.
Interview Process
1 round
1 round, panel interview with 2-3 interviewers
Duration: 1 hour
Focus: Q&A covering diffractive optics, hands-on experimental experience, and discussion of the candidate's PhD work
#J-18808-Ljbffr
Duration: 24 Months
Location: Onsite in Redmond /WA
Responsibilities
Design and develop complete Photonic Integrated Circuits (PICs), from fundamental component blocks to full-circuit implementations, with a strong emphasis on active device integration.
Generate, verify, and prepare fabrication-ready layout files, ensuring compliance with foundry PDks (Process Design Kits) for external fabrication.
Conduct systematic design analysis, including optimization and parametric studies, to guide design decisions.
Support the entire design-to-fabrication pipeline, from initial concept through tapeout, coordinating closely with cross-functional teams and external partners.
Collaborate with program leadership, Technical Program Managers (TPMs), and researchers on PIC designs that align with overall program objectives.
Must-Have Skills
PIC Design & Simulation: 3+ years designing, simulating, and laying out photonic integrated circuits (PICs) for visible/IR wavelengths.
Photonic Modeling Tools: Proficiency with tools like Lumerical, Ansys Photonics, Synopsys RSoft, or COMSOL for device/circuit analysis.
PIC Layout & Tapeout: Experience with layout tools (KLayout, Cadence Virtuoso, gdsfactory), GDSII generation, and supporting tapeouts at commercial foundries.
Nice-to-Have Skills
Active PIC Design & Validation: Experience in active PIC design, fabrication, and validation, especially for visible wavelengths.
Device Characterization: Skills in optical/electro-optic measurements, fiber optics, free-space optics, and PIC packaging.
Statistical Modeling & Sensitivity Analysis: Experience in design space exploration, yield modeling, and incorporating fabrication constraints.
Minimum Qualifications
MS or Ph.D. degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
3+ years of hands-on experience in the design, simulation, and layout of PICs for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.
3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).
2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.
2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.
1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).
Preferred Qualifications
3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.
3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.
3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).
2+ years of experience utilizing photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.
2+ years of experience in photonic device characterization and test, including both optical and electro-optic measurements.
1+ years experience with fiber optics, free-space optics, PIC packaging, and comprehensive device characterization.
1+ years experience with semiconductor fabrication processes and a deep understanding of process-induced performance limitations, such as optical losses, sidewall roughness, and process variability.
Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementing effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).
Minimum Years of Experience
5-7
Degrees/Certifications
Required: MS or Ph.D. degree (preferred) in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
Key Projects / Day-to-Day Responsibilities
Design, simulate, and optimize PICs and photonic devices.
Prepare fabrication-ready layouts and ensure compliance with foundry PDKs.
Analyze and improve designs through parametric studies.
Coordinate the design-to-fabrication pipeline with cross-functional teams and external partners. Collaborate with leadership and researchers to align designs with program goals.
Purpose / Size of This Team & Role
Key technical contributor in the R&D team, collaborating with leadership, TPMs, and researchers. Drives PIC design and fabrication efforts, bridging technical and program objectives.
Projects / Products
Developing advanced photonic integrated circuits for next-gen near-to-eye display systems. Integrating active devices and optimizing for fabrication constraints. Improving system-level performance and yield through design analysis and modeling.
About the Team
R&D team focused on cutting-edge near-to-eye display systems. Multidisciplinary collaboration with engineers, researchers, and program managers. Drives innovation in integrated photonics and display technology.
Progress Metrics
Successful design and tapeout of PICs.
Quality and innovation in device simulation, layout, and fabrication.
Effective collaboration and alignment with program goals.
Ability to optimize designs for performance and manufacturability.
Challenges & How to Address Them
Overcoming challenges like optical losses, process variability, and device packaging.
Why This Role Appeals
Opportunity to work on cutting-edge photonics for next-generation display technology.
Collaborate with top experts in a highly innovative R&D environment.
Direct impact on product development and technology advancement.
Interview Process
1 round
1 round, panel interview with 2-3 interviewers
Duration: 1 hour
Focus: Q&A covering diffractive optics, hands-on experimental experience, and discussion of the candidate's PhD work
#J-18808-Ljbffr