SoC Physical Design Engineer - From Netlist to Tapeout

A leading technology company in San Jose is seeking an experienced professional for a chip design role focused on implementing complete design from netlist to tapeout. The ideal candidate will have over 10 years of experience, a BS degree, and a deep understanding of ASIC integration and physical design methodologies. The position offers a competitive base pay range between $147,400 and $272,100, plus attractive benefits including medical coverage and stock options.
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