Senior CAD Design Verification Engineer (DV Methodology)

A leading technology company is seeking an experienced software engineer to join their CAD team in Austin, Texas, focusing on developing and enhancing systems for regression-testing silicon designs. The ideal candidate has a BS degree with at least 10 years of relevant experience and a strong background in Python programming. Candidates with knowledge of Verilog and experience with EDA tools like Synopsys VCS will find a fulfilling role within this collaborative team dedicated to innovation.
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