Silicon Design Engineer
Advanced Micro Devices, San Jose, CA, United States
Role
Silicon Design Verification Engineer – AMD SOC Verification Team.
Key Responsibilities
Work with senior verification engineers and create test plans for complex IP designs.
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner.
Create and enhance constrained‑random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry‑leading formal tools.
Debug tests with design engineers to deliver functionally correct design blocks and close the coverage.
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.
Responsible for verification quality metrics like pass rates, code coverage, and functional coverage.
Preferred Experience
Project level experience with design concepts and RTL implementation.
Good understanding of computer organization/architecture and digital logic fundamentals.
Knowledge of object‑oriented concepts and programming languages such as System Verilog, C++.
Hands‑on Python scripting for automation.
Prior design/verification industry experience, especially UVM.
Academic Credentials
Master’s degree in Computer Engineering, Electrical Engineering, or related discipline.
Location
San Jose, CA
This role is not eligible for visa sponsorship.
AMD is an equal opportunity, inclusive employer and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under all applicable laws.
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Silicon Design Verification Engineer – AMD SOC Verification Team.
Key Responsibilities
Work with senior verification engineers and create test plans for complex IP designs.
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner.
Create and enhance constrained‑random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry‑leading formal tools.
Debug tests with design engineers to deliver functionally correct design blocks and close the coverage.
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.
Responsible for verification quality metrics like pass rates, code coverage, and functional coverage.
Preferred Experience
Project level experience with design concepts and RTL implementation.
Good understanding of computer organization/architecture and digital logic fundamentals.
Knowledge of object‑oriented concepts and programming languages such as System Verilog, C++.
Hands‑on Python scripting for automation.
Prior design/verification industry experience, especially UVM.
Academic Credentials
Master’s degree in Computer Engineering, Electrical Engineering, or related discipline.
Location
San Jose, CA
This role is not eligible for visa sponsorship.
AMD is an equal opportunity, inclusive employer and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under all applicable laws.
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