Sr. Staff Engineer, Analog/Mixed Signal Design
Ayar Labs, San Jose, CA, United States
Position: Sr. Staff Engineer, Analog/Mixed Signal Design
Location: San Jose, CA (on-site)
Job Id: 537
# of Openings: 0
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co‑packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co‑packaged optics solution is key to unleashing next‑generation AI scale‑up architectures.
As an Analog and Mixed Signal Design Engineer, you will design various blocks such as oscillators, high speed transmitters/receivers, biasing circuits, linear regulators, ADCs/DACs, and others. You will work as a part of a small IC design team in a dynamic startup environment. The ideal candidate is a hands‑on self‑starter who is able to develop design specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
Key Responsibilities
Architect and design high speed signal path for high bandwidth optical links
Work closely with optical and digital design teams to architect mixed‑signal control loops
Design analog/mixed signal circuits such as oscillators, high speed transmitters/receivers, amplifiers, biasing circuits, linear regulators, ADCs/DACs, and others
Define, run, and automate sign‑off verification simulations
Create design review and testing documentation
Perform post‑silicon bring‑up of circuits in lab
Required Qualifications
M.S. or Ph.D. in Electrical Engineering
6+ years of work experience in analog/mixed signal design
Experience designing high speed analog blocks such as PLLs, clock distribution and multi‑phase generation, high swing transmit drivers, high speed receive analog front ends.
Proficient with Cadence design environment and mixed‑signal simulation (ADE, Layout, Spectre)
Have experience designing in FinFet CMOS (7nm or below) at data rates of at least 50 Gb/s and/or RF circuits operating at 25 GHz or above
Preferred Qualifications
Demonstrated experience in deploying SerDes into a high‑volume product
A good understanding of high‑speed design/layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc.
Experience with silicon bring‑up, debug, and evaluation
Programming experience in Python and SKILL
Salary range: $180,000 – $223,000
NOTE TO RECRUITERS
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an affirmative action/equal opportunity employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
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Location: San Jose, CA (on-site)
Job Id: 537
# of Openings: 0
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co‑packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co‑packaged optics solution is key to unleashing next‑generation AI scale‑up architectures.
As an Analog and Mixed Signal Design Engineer, you will design various blocks such as oscillators, high speed transmitters/receivers, biasing circuits, linear regulators, ADCs/DACs, and others. You will work as a part of a small IC design team in a dynamic startup environment. The ideal candidate is a hands‑on self‑starter who is able to develop design specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
Key Responsibilities
Architect and design high speed signal path for high bandwidth optical links
Work closely with optical and digital design teams to architect mixed‑signal control loops
Design analog/mixed signal circuits such as oscillators, high speed transmitters/receivers, amplifiers, biasing circuits, linear regulators, ADCs/DACs, and others
Define, run, and automate sign‑off verification simulations
Create design review and testing documentation
Perform post‑silicon bring‑up of circuits in lab
Required Qualifications
M.S. or Ph.D. in Electrical Engineering
6+ years of work experience in analog/mixed signal design
Experience designing high speed analog blocks such as PLLs, clock distribution and multi‑phase generation, high swing transmit drivers, high speed receive analog front ends.
Proficient with Cadence design environment and mixed‑signal simulation (ADE, Layout, Spectre)
Have experience designing in FinFet CMOS (7nm or below) at data rates of at least 50 Gb/s and/or RF circuits operating at 25 GHz or above
Preferred Qualifications
Demonstrated experience in deploying SerDes into a high‑volume product
A good understanding of high‑speed design/layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc.
Experience with silicon bring‑up, debug, and evaluation
Programming experience in Python and SKILL
Salary range: $180,000 – $223,000
NOTE TO RECRUITERS
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an affirmative action/equal opportunity employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
#J-18808-Ljbffr