Lead RTL Design & Verification Engineer (AMS/IO)

A leading technology company in Chandler, Arizona, is seeking an RTL Design Engineer to lead the digital design and verification of analog mixed-signal IP and IOs. This role requires a minimum of 10 years of experience and proficiency in Verilog/SystemVerilog, scripting languages like Perl, Python, and Tcl. Strong problem-solving skills and collaboration with cross-functional teams are vital for success. Competitive benefits include medical plans, a 401(K), and an annual bonus.
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