Senior Design Verification Engineer – UVM Expert

A leading technology firm in Sunnyvale, California is seeking a Sr Design Verification Engineer with extensive experience in ASIC verification. Responsibilities include developing UVM/SystemVerilog testbenches, creating test plans, and collaborating across teams to ensure design integrity. Ideal candidates should possess over 10 years of experience, strong SystemVerilog and UVM skills, and proficiency in Python scripting. The role offers a competitive compensation package including salary and benefits.
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