SOC Design Engineer
Intel, Santa Clara, CA, United States
Job Details
The job develops logic design, RTL coding, and simulation for graphics IPs required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. It participates in definition of architecture and microarchitecture features, applies tools and strategies to write RTL and optimize logic to meet power, performance, area, and timing goals, and ensures design integrity for physical implementation. It reviews verification plans, drives unit level verification, and resolves RTL test failures to ensure correctness. It supports SoC customers to ensure high quality integration of the GPU block.
Responsibilities
Design and integrate IP for a discrete graphics SoC.
Assist in architecture, design, implementation, formal verification, emulation, and validation of discrete graphics SoC products.
Create designs that improve product KPIs.
Collaborate with SoC Architecture and platform architecture teams to establish silicon requirements.
Make design trade‑offs balancing risk, area, power, performance, validation complexity, and schedule.
Create microarchitectural specification documents.
Work with external vendors on tools or IPs for micro‑architecture design and qualification.
Drive vendor methodology to meet world‑class silicon design standards.
Architect area‑ and power‑efficient, low‑latency designs with scalability and flexibility.
Provide power and area efficient RTL logic design and DV support.
Run tools to ensure lint‑free and CDC/RDC clean design.
Define synthesis and timing constraints.
The ideal candidate
Ability to drive and improve digital design methodology to achieve high quality first silicon.
Experience working with cross‑functional teams within Intel and external vendors across geographic boundaries.
Strong verbal and written communication skills.
Qualifications
Minimum
B.S. in Electrical or Computer Engineering with 4+ years experience in the semiconductor industry.
or M.S. in Electrical or Computer Engineering with 3+ years experience.
4+ years experience in Verilog/SystemVerilog, synthesizable RTL, modern design techniques, energy‑efficient/low‑power logic design, power analysis, computer architecture, or GPU.
Preferred
Experience with FPGA emulation, silicon bring‑up, characterization, and debug.
Experience in multiple tape‑outs reaching production with first‑pass silicon.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, California, Folsom
Additional Locations
US, California, Santa Clara
Business Group
Chief Technology Office, Artificial Intelligence, and Network and Edge Group (CTO AI NEX) focuses on AI market penetration and transforming global networks.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
Competitive pay, stock bonuses, health, retirement, and vacation. Annual salary range: $164,470.00 – 311,890.00 USD. Compensation determined by location and factors such as experience.
Work Model
On‑site presence required.
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The job develops logic design, RTL coding, and simulation for graphics IPs required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. It participates in definition of architecture and microarchitecture features, applies tools and strategies to write RTL and optimize logic to meet power, performance, area, and timing goals, and ensures design integrity for physical implementation. It reviews verification plans, drives unit level verification, and resolves RTL test failures to ensure correctness. It supports SoC customers to ensure high quality integration of the GPU block.
Responsibilities
Design and integrate IP for a discrete graphics SoC.
Assist in architecture, design, implementation, formal verification, emulation, and validation of discrete graphics SoC products.
Create designs that improve product KPIs.
Collaborate with SoC Architecture and platform architecture teams to establish silicon requirements.
Make design trade‑offs balancing risk, area, power, performance, validation complexity, and schedule.
Create microarchitectural specification documents.
Work with external vendors on tools or IPs for micro‑architecture design and qualification.
Drive vendor methodology to meet world‑class silicon design standards.
Architect area‑ and power‑efficient, low‑latency designs with scalability and flexibility.
Provide power and area efficient RTL logic design and DV support.
Run tools to ensure lint‑free and CDC/RDC clean design.
Define synthesis and timing constraints.
The ideal candidate
Ability to drive and improve digital design methodology to achieve high quality first silicon.
Experience working with cross‑functional teams within Intel and external vendors across geographic boundaries.
Strong verbal and written communication skills.
Qualifications
Minimum
B.S. in Electrical or Computer Engineering with 4+ years experience in the semiconductor industry.
or M.S. in Electrical or Computer Engineering with 3+ years experience.
4+ years experience in Verilog/SystemVerilog, synthesizable RTL, modern design techniques, energy‑efficient/low‑power logic design, power analysis, computer architecture, or GPU.
Preferred
Experience with FPGA emulation, silicon bring‑up, characterization, and debug.
Experience in multiple tape‑outs reaching production with first‑pass silicon.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, California, Folsom
Additional Locations
US, California, Santa Clara
Business Group
Chief Technology Office, Artificial Intelligence, and Network and Edge Group (CTO AI NEX) focuses on AI market penetration and transforming global networks.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
Competitive pay, stock bonuses, health, retirement, and vacation. Annual salary range: $164,470.00 – 311,890.00 USD. Compensation determined by location and factors such as experience.
Work Model
On‑site presence required.
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