Lead Cache Coherency Architect: NoC & IP Co-design (Equity)

A leading semiconductor company is looking for a Senior Cache Coherency Architect in Santa Clara, CA. This role involves defining interconnect architecture and cache-coherency protocols and collaborating with architects to meet project requirements. Candidates should have a Master's degree, 5+ years of experience in processor design, and strong understanding of cache coherency protocols. The position offers a competitive base salary range between 152,000 USD - 287,500 USD, eligible for equity, and applications accepted until April 24, 2026.
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