ASIC Digital Design, RTL - 16908
Synopsys, Boxborough, MA, United States
Date posted
04/09/2026
Category
Engineering
Hire Type
Employee
Job ID
16908
Base Salary Range
$138000-$208000
Remote Eligible
No
Date Posted
04/09/2026
We Are:
At Synopsys, we drive innovations that shape how the world connects and lives. Our technology powers chip design, verification, and IP integration. Join us to transform the future through continuous technological innovation.
You Are:
You are an experienced digital designer with deep expertise in high-speed interconnects. You thrive in collaborative, global teams and enjoy mentoring others. Your technical skills and problem-solving mindset help shape industry-leading solutions. You're eager to contribute to cutting-edge chiplet systems and advance your career in a dynamic environment.
What You'll Be Doing:
Designing high-performance digital logic for Die to Die IP
Collaborating across teams on PHY and controller designs
Optimizing IP for performance, power, and area
Participating in the full Hard IP design cycle
Providing technical guidance to junior engineers
Staying current with industry trends
The Impact You Will Have:
Driving world-class D2D IP development
Shaping semiconductor technology's future
Ensuring high-quality IP delivery
Enhancing Synopsys IP adoption
Mentoring engineers globally
Strengthening Synopsys' leadership
What You'll Need:
Expertise in SerDes, DDR/HBM, or UCIe PHY
Hard IP design experience
Proficiency in SystemVerilog
Strong RTL-to-gate design flow knowledge
Excellent problem-solving and communication skills
Who You Are:
Collaborative and inclusive
Analytical and detail-oriented
Effective communicator
Mentor and leader
The Team You'll Be A Part Of:
Join a diverse, world-class engineering team focused on high-speed Die to Die IP innovation in a global, matrixed environment.
Rewards and Benefits:
We offer comprehensive health, wellness, and financial benefits. Your recruiter will share more about salary and perks during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
04/09/2026
Category
Engineering
Hire Type
Employee
Job ID
16908
Base Salary Range
$138000-$208000
Remote Eligible
No
Date Posted
04/09/2026
We Are:
At Synopsys, we drive innovations that shape how the world connects and lives. Our technology powers chip design, verification, and IP integration. Join us to transform the future through continuous technological innovation.
You Are:
You are an experienced digital designer with deep expertise in high-speed interconnects. You thrive in collaborative, global teams and enjoy mentoring others. Your technical skills and problem-solving mindset help shape industry-leading solutions. You're eager to contribute to cutting-edge chiplet systems and advance your career in a dynamic environment.
What You'll Be Doing:
Designing high-performance digital logic for Die to Die IP
Collaborating across teams on PHY and controller designs
Optimizing IP for performance, power, and area
Participating in the full Hard IP design cycle
Providing technical guidance to junior engineers
Staying current with industry trends
The Impact You Will Have:
Driving world-class D2D IP development
Shaping semiconductor technology's future
Ensuring high-quality IP delivery
Enhancing Synopsys IP adoption
Mentoring engineers globally
Strengthening Synopsys' leadership
What You'll Need:
Expertise in SerDes, DDR/HBM, or UCIe PHY
Hard IP design experience
Proficiency in SystemVerilog
Strong RTL-to-gate design flow knowledge
Excellent problem-solving and communication skills
Who You Are:
Collaborative and inclusive
Analytical and detail-oriented
Effective communicator
Mentor and leader
The Team You'll Be A Part Of:
Join a diverse, world-class engineering team focused on high-speed Die to Die IP innovation in a global, matrixed environment.
Rewards and Benefits:
We offer comprehensive health, wellness, and financial benefits. Your recruiter will share more about salary and perks during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.