DFT Design Engineer, Machine Learning Acceleration
Amazon, Austin, TX, United States
DFT Design Engineer, Machine Learning Acceleration
Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems – our custom‑designed machine learning inference and training servers. Our success depends on world‑class server infrastructure as we handle massive scale and rapidly integrate emerging technologies.
Key Job Responsibilities
Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes.
Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions.
Perform RTL coding and verification using Verilog/SystemVerilog.
Utilize industry‑standard DFT tools to create high‑coverage, cost‑effective test patterns targeting advanced silicon defects.
Participate in silicon debug efforts alongside ATE and System teams.
Communicate and work with team members across multiple disciplines.
Basic Qualifications
Bachelor's degree in Electrical or Communications Engineering or a related field.
5+ years of practical DFT experience with complex SoC designs in advanced technology nodes.
Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade‑offs between test quality and test time.
Experience with automation script development.
Preferred Qualifications
Master's degree in Electrical or Communications Engineering or a related field.
Practical experience developing STA constraints for DFT modes and working directly with PD teams to close timing.
Experience with RTL coding and design verification (DV) flows.
Experience with gate‑level simulation setup and debug with SDF.
Strong programming and scripting skills in Perl, Python or Tcl.
Practical experience with silicon debug and yield optimization.
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. Our inclusive culture empowers Amazonians to deliver the best results for our customers.
Location: Austin, TX, USA – Salary: 136,000.00 – 184,000.00 USD annually. Benefits include health insurance, 401(k) matching, paid time off, parental leave, and more. Learn more about our benefits at https://amazon.jobs/en/benefits.
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Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems – our custom‑designed machine learning inference and training servers. Our success depends on world‑class server infrastructure as we handle massive scale and rapidly integrate emerging technologies.
Key Job Responsibilities
Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes.
Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions.
Perform RTL coding and verification using Verilog/SystemVerilog.
Utilize industry‑standard DFT tools to create high‑coverage, cost‑effective test patterns targeting advanced silicon defects.
Participate in silicon debug efforts alongside ATE and System teams.
Communicate and work with team members across multiple disciplines.
Basic Qualifications
Bachelor's degree in Electrical or Communications Engineering or a related field.
5+ years of practical DFT experience with complex SoC designs in advanced technology nodes.
Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade‑offs between test quality and test time.
Experience with automation script development.
Preferred Qualifications
Master's degree in Electrical or Communications Engineering or a related field.
Practical experience developing STA constraints for DFT modes and working directly with PD teams to close timing.
Experience with RTL coding and design verification (DV) flows.
Experience with gate‑level simulation setup and debug with SDF.
Strong programming and scripting skills in Perl, Python or Tcl.
Practical experience with silicon debug and yield optimization.
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. Our inclusive culture empowers Amazonians to deliver the best results for our customers.
Location: Austin, TX, USA – Salary: 136,000.00 – 184,000.00 USD annually. Benefits include health insurance, 401(k) matching, paid time off, parental leave, and more. Learn more about our benefits at https://amazon.jobs/en/benefits.
#J-18808-Ljbffr