RISC-V Frontend RTL Design Engineer — Equity & Benefits

A leading semiconductor company in Santa Clara is seeking a talented CPU Core Engineer to design and implement RISC-V CPU core features. You will work with various teams to integrate designs into the Chisel framework and ensure high-quality outcomes. The ideal candidate has a strong background in CPU RTL design, programming skills in relevant languages, and a collaborative mindset. The position includes a competitive salary range of $158,760 to $194,040 depending on experience, along with a comprehensive benefits package.
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