ASIC Chip Design Lead
Eridu, Saratoga, CA, United States
About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company’s solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co‑founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro‑LED company). The company is in execution mode and has a world‑class engineering team with decades of experience in state‑of‑the‑art silicon, packaging, optics, software, and systems. Eridu is working with best‑in‑class supply chain partners including silicon, packaging and systems.
Position Overview
We are seeking a hands‑on ASIC Chip Design Lead to own chip design execution from micro‑architecture through full‑chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro‑architecture while providing execution leadership across design, verification, and physical design teams.
This is a highly technical, roll‑up‑your‑sleeves role for someone who has taken chips to tape‑out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast‑paced startup environment.
Responsibilities
Write, review, and debug production‑quality RTL in Verilog/SystemVerilog
Own RTL blocks end‑to‑end from specification through signoff
Make timing‑, area‑, and power‑aware design decisions at the RTL and micro‑architecture levels
Perform detailed code reviews and set a high technical bar for RTL quality
Draft detailed micro‑architecture specifications derived from architecture documents and feature requirements
Translate high‑level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner‑case handling
Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution
Work closely with Physical Design to improve synthesis and place‑and‑route timing.
Iterate on RTL, hierarchy, micro‑architecture, and floorplanning to address timing, congestion, and QoR issues
Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements
Partner with Design Verification to debug functional and performance issues
Review functional and code coverage and provide actionable feedback
Own bugs from discovery through fix, validation, and closure
Own full‑chip RTL integration and block roll‑up
Run chip‑level synthesis, define constraints, and close chip‑level timing
Deliver timing‑clean netlists to Physical Design that meet performance targets
Drive block‑ and chip‑level design checklists as execution quality gates
Review checklist status with designers and proactively push closure of open items
Continuously refine design methodologies, checklists, and flows based on silicon learnings
Lead by technical authority and hands‑on execution rather than coordination alone
Qualifications
Strong hands‑on experience with RTL design and micro‑architecture
Proven experience with full‑chip integration and timing closure
Led at least one full‑chip tape‑out within the last 3 years, with direct responsibility for design signoff and PD handoff
Deep understanding of synthesis, static timing analysis, and physical‑design collaboration
Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
Comfortable working cross‑functionally with architecture, verification, firmware, and physical design teams
Demonstrated ability to drive execution in ambiguous, fast‑moving environments
Nice to Have
Silicon bring‑up experience, including post‑silicon debug and RTL‑to‑silicon correlation
Hands‑on experience defining and refining SDC constraints and improving post‑layout timing
Knowledge of high‑performance networking architectures and Ethernet‑based systems
Familiarity with Ultra Ethernet and/or UCIe chip‑to‑chip interconnect protocols
Experience with chiplet‑based system design
Why Join Us?
At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
The Pay Range For This Role Is
250,000 - 280,000 USD per year (Saratoga, CA)
#J-18808-Ljbffr
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company’s solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co‑founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro‑LED company). The company is in execution mode and has a world‑class engineering team with decades of experience in state‑of‑the‑art silicon, packaging, optics, software, and systems. Eridu is working with best‑in‑class supply chain partners including silicon, packaging and systems.
Position Overview
We are seeking a hands‑on ASIC Chip Design Lead to own chip design execution from micro‑architecture through full‑chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro‑architecture while providing execution leadership across design, verification, and physical design teams.
This is a highly technical, roll‑up‑your‑sleeves role for someone who has taken chips to tape‑out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast‑paced startup environment.
Responsibilities
Write, review, and debug production‑quality RTL in Verilog/SystemVerilog
Own RTL blocks end‑to‑end from specification through signoff
Make timing‑, area‑, and power‑aware design decisions at the RTL and micro‑architecture levels
Perform detailed code reviews and set a high technical bar for RTL quality
Draft detailed micro‑architecture specifications derived from architecture documents and feature requirements
Translate high‑level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner‑case handling
Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution
Work closely with Physical Design to improve synthesis and place‑and‑route timing.
Iterate on RTL, hierarchy, micro‑architecture, and floorplanning to address timing, congestion, and QoR issues
Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements
Partner with Design Verification to debug functional and performance issues
Review functional and code coverage and provide actionable feedback
Own bugs from discovery through fix, validation, and closure
Own full‑chip RTL integration and block roll‑up
Run chip‑level synthesis, define constraints, and close chip‑level timing
Deliver timing‑clean netlists to Physical Design that meet performance targets
Drive block‑ and chip‑level design checklists as execution quality gates
Review checklist status with designers and proactively push closure of open items
Continuously refine design methodologies, checklists, and flows based on silicon learnings
Lead by technical authority and hands‑on execution rather than coordination alone
Qualifications
Strong hands‑on experience with RTL design and micro‑architecture
Proven experience with full‑chip integration and timing closure
Led at least one full‑chip tape‑out within the last 3 years, with direct responsibility for design signoff and PD handoff
Deep understanding of synthesis, static timing analysis, and physical‑design collaboration
Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
Comfortable working cross‑functionally with architecture, verification, firmware, and physical design teams
Demonstrated ability to drive execution in ambiguous, fast‑moving environments
Nice to Have
Silicon bring‑up experience, including post‑silicon debug and RTL‑to‑silicon correlation
Hands‑on experience defining and refining SDC constraints and improving post‑layout timing
Knowledge of high‑performance networking architectures and Ethernet‑based systems
Familiarity with Ultra Ethernet and/or UCIe chip‑to‑chip interconnect protocols
Experience with chiplet‑based system design
Why Join Us?
At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
The Pay Range For This Role Is
250,000 - 280,000 USD per year (Saratoga, CA)
#J-18808-Ljbffr