Senior FPGA RTL Design Engineer - Silicon Bring-Up

A leading technology firm is seeking an FPGA Silicon Design Engineer in San Jose, California. The role involves developing high-quality logic designs and RTL implementations for FPGA products. Candidates should hold a Bachelor's degree in a relevant field and possess over 8 years of experience in RTL design and coding. Key responsibilities include debugging RTL tests and collaborating with cross-functional teams to achieve power, performance, and area targets. The salary range for this position is $149,100 - $215,925 USD.
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