MEMS Design Engineer
ALKU, Durham, NC, United States
Our client is seeking an experienced Design Engineer with a strong memory-interface background to support fast-moving development efforts on high-speed memory subsystems. This team is looking for someone who has worked directly on memory controllers, PHYs, or related interface logic and can contribute in a hands-on environment with minimal ramp-up.
Project The engineer will support the design and implementation of memory-interface logic tied to DDR, LPDDR, HBM, or related architectures. The work will likely involve controller and/or PHY development, interface integration, timing and latency considerations, and close collaboration with adjacent design and verification teams. There is also interest in candidates with some coding or scripting experience to support debug, modeling, automation, or development efficiency.
Required Skills 5+ years of digital design engineering experience
Strong background with memory interfaces such as DDR, LPDDR, HBM, GDDR, or similar
Experience with memory controller and/or PHY design
Strong RTL design skills in Verilog and/or SystemVerilog
Experience integrating high-speed interface logic into complex SoC or subsystem environments
Familiarity with timing, CDC, resets, training/calibration flows, and interface-level debug
Some coding or scripting experience in Python, Perl, Tcl, shell, or C/C++
Ability to work effectively in a fast-paced development environment
Nice to Have Experience with advanced packaging, memory product engineering, or HBM-related implementations
Exposure to memory-chip behavior, signal integrity, or package-related reliability concerns
Experience with bring-up, lab debug, or silicon validation tied to memory subsystems
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Project The engineer will support the design and implementation of memory-interface logic tied to DDR, LPDDR, HBM, or related architectures. The work will likely involve controller and/or PHY development, interface integration, timing and latency considerations, and close collaboration with adjacent design and verification teams. There is also interest in candidates with some coding or scripting experience to support debug, modeling, automation, or development efficiency.
Required Skills 5+ years of digital design engineering experience
Strong background with memory interfaces such as DDR, LPDDR, HBM, GDDR, or similar
Experience with memory controller and/or PHY design
Strong RTL design skills in Verilog and/or SystemVerilog
Experience integrating high-speed interface logic into complex SoC or subsystem environments
Familiarity with timing, CDC, resets, training/calibration flows, and interface-level debug
Some coding or scripting experience in Python, Perl, Tcl, shell, or C/C++
Ability to work effectively in a fast-paced development environment
Nice to Have Experience with advanced packaging, memory product engineering, or HBM-related implementations
Exposure to memory-chip behavior, signal integrity, or package-related reliability concerns
Experience with bring-up, lab debug, or silicon validation tied to memory subsystems
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