ESD & Latch-Up Design Engineer for CMOS ICs

A leading semiconductor company in Boise, Idaho is seeking a talented ESD/LUP Research Engineer to lead innovative design solutions that minimize product defects from electrostatic discharge events. The ideal candidate will have a strong background in semiconductor physics and experience with Cadence design tools. This position requires excellent data analysis and communication skills to collaborate effectively across teams. Join us to advance cutting-edge memory solutions and technology!
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