IP Logic Design Engineer
Solidigm, Rancho Cordova, CA, United States
Company Description Join a multibillion-dollar global company that brings together technology, people, and operational scale to lead in the memory industry. Solidigm is headquartered in Rancho Cordova, California, with an international presence in Asia, Europe, and the Americas. We foster a diverse, equitable, and inclusive culture that empowers us to deliver excellence in support of Solidigm's vision and mission to be a go-to partner for optimized data storage solutions.
Job Description Join Solidigm’s Design Engineering Team as a 3D NAND IP Logic Design Engineer and help shape the future of memory technology.
Job responsibilities include, but are not limited to:
Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components
Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with appropriate constraints, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off
Develop and optimize microcode-based 3D NAND algorithms (read, program, erase, power-on) using proprietary instruction sets and compilers
Contribute to next-gen 3D NAND architecture and pathfinding to improve density, die-size, performance, power, and cost
Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), run full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer features
Review pre-silicon analog and mixed signal (AMS) simulations and post-silicon microprobe waveforms to conduct power & performance modeling and ensure the functionality of various digital & analog blocks
Partner with product engineering and technology development teams to define Read-Window-Budget (RWB) features and develop Design for Testability (DFT) methods that reduce test time and cost while improving quality
Support post-silicon debug and failure analysis across multiple configurations
Qualifications MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience
Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO
Experience with lint tools, CDC/RDC analysis, and timing constraints
Strong background in design verification tools and automation scripting
Prior experience in 3D NAND Flash Memory logic design is a plus
Ability to work independently across pre- and post-silicon debug cycles
Additional Information The compensation range for this role is $121,280 - $194,100. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.
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Job Description Join Solidigm’s Design Engineering Team as a 3D NAND IP Logic Design Engineer and help shape the future of memory technology.
Job responsibilities include, but are not limited to:
Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components
Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with appropriate constraints, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off
Develop and optimize microcode-based 3D NAND algorithms (read, program, erase, power-on) using proprietary instruction sets and compilers
Contribute to next-gen 3D NAND architecture and pathfinding to improve density, die-size, performance, power, and cost
Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), run full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer features
Review pre-silicon analog and mixed signal (AMS) simulations and post-silicon microprobe waveforms to conduct power & performance modeling and ensure the functionality of various digital & analog blocks
Partner with product engineering and technology development teams to define Read-Window-Budget (RWB) features and develop Design for Testability (DFT) methods that reduce test time and cost while improving quality
Support post-silicon debug and failure analysis across multiple configurations
Qualifications MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience
Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO
Experience with lint tools, CDC/RDC analysis, and timing constraints
Strong background in design verification tools and automation scripting
Prior experience in 3D NAND Flash Memory logic design is a plus
Ability to work independently across pre- and post-silicon debug cycles
Additional Information The compensation range for this role is $121,280 - $194,100. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.
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