Sr. ASIC Layout Design Engineer
Teledyne Technologies Incorporated, Goleta, CA, United States
Job Description
Job Summary: We are seeking an experienced Senior Analog/Mixed‑Signal Layout Design Engineer to develop high‑performance focal‑plane array readout integrated circuits (ROICs). These chips power infrared detectors, sensors, and cameras used in diverse applications ranging from firefighting and security to scientific research and government contracts. You will prepare detailed, multi‑dimensional circuit layouts from schematics, collaborate with analog and digital designers to ensure signal integrity, and support the entire design flow from discussion to tape‑out, shaping industry‑leading imaging technology.
Primary Duties & Responsibilities
Develop high‑quality analog/mixed‑signal IC layouts and create GDS databases of completed designs using Cadence and Siemens software tools.
Collaborate with circuit designers to optimize floor‑planning, placement, and routing.
Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Parasitic Extraction (PEX), and the use of Process Design Kits (PDK).
Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance, manufacturability, and yield.
Present weekly updates to project schedule and percent task completions. Prepare reports for design reviews and internal and external customer presentations.
Perform proper handling of Export Controlled Information and exercise discipline in following GTC protocol and jurisdictional classification.
Release and maintain design documents per the ISO quality system requirements.
Must be US Citizen or PERM Resident
Applicants must be US citizens or lawful permanent residents.
What You Bring
Bachelor’s degree in engineering or related field with 10+ years of industry experience.
Expertise in analog/mixed‑signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm process nodes.
Proficiency in Cadence Virtuoso XL for connectivity‑aware design.
Strong understanding of Calibre verification (DRC, LVS) and troubleshooting techniques.
Experience with custom cell‑based layout and top‑level floor planning; work on focal‑plane arrays a plus.
Technical knowledge of wire resistance, coupling capacitance, and best practices for minimizing parasitic effects.
Excellent communication skills and the ability to work effectively within a multidisciplinary team.
Programming/scripting skills in SKILL, TCL, Shell, or Python.
Salary Range
$113,600 – $151,400
Pay Transparency
The anticipated salary range listed for this role is an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, local regulations (such as minimum wage), education/training, work experience, key skills, and type of position.
Teledyne is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, age, or any other characteristic or non‑merit based factor made unlawful by federal, state, or local laws.
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Job Summary: We are seeking an experienced Senior Analog/Mixed‑Signal Layout Design Engineer to develop high‑performance focal‑plane array readout integrated circuits (ROICs). These chips power infrared detectors, sensors, and cameras used in diverse applications ranging from firefighting and security to scientific research and government contracts. You will prepare detailed, multi‑dimensional circuit layouts from schematics, collaborate with analog and digital designers to ensure signal integrity, and support the entire design flow from discussion to tape‑out, shaping industry‑leading imaging technology.
Primary Duties & Responsibilities
Develop high‑quality analog/mixed‑signal IC layouts and create GDS databases of completed designs using Cadence and Siemens software tools.
Collaborate with circuit designers to optimize floor‑planning, placement, and routing.
Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Parasitic Extraction (PEX), and the use of Process Design Kits (PDK).
Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance, manufacturability, and yield.
Present weekly updates to project schedule and percent task completions. Prepare reports for design reviews and internal and external customer presentations.
Perform proper handling of Export Controlled Information and exercise discipline in following GTC protocol and jurisdictional classification.
Release and maintain design documents per the ISO quality system requirements.
Must be US Citizen or PERM Resident
Applicants must be US citizens or lawful permanent residents.
What You Bring
Bachelor’s degree in engineering or related field with 10+ years of industry experience.
Expertise in analog/mixed‑signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm process nodes.
Proficiency in Cadence Virtuoso XL for connectivity‑aware design.
Strong understanding of Calibre verification (DRC, LVS) and troubleshooting techniques.
Experience with custom cell‑based layout and top‑level floor planning; work on focal‑plane arrays a plus.
Technical knowledge of wire resistance, coupling capacitance, and best practices for minimizing parasitic effects.
Excellent communication skills and the ability to work effectively within a multidisciplinary team.
Programming/scripting skills in SKILL, TCL, Shell, or Python.
Salary Range
$113,600 – $151,400
Pay Transparency
The anticipated salary range listed for this role is an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, local regulations (such as minimum wage), education/training, work experience, key skills, and type of position.
Teledyne is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, age, or any other characteristic or non‑merit based factor made unlawful by federal, state, or local laws.
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