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Senior C++ FPGA Prototyping Engineer

Cadence Design Systems, Inc., San Jose, CA, United States


A global electronic design automation company in San Jose, California is seeking a C++ software engineer to enhance FPGA-based products for pre-Silicon validation. The ideal candidate will have expertise in C/C++, experience with Verilog/SystemVerilog, and a background in FPGA or ASIC development. This role offers a competitive salary range of $110,600 to $205,400 along with incentives and comprehensive benefits.
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