Hybrid Principal Verification Engineer — Lead Full-Chip UVM

A leading chip and silicon IP provider is seeking a Principal Verification Engineer in San Jose, CA. This full-time hybrid role involves leading verification strategies and working alongside talented engineers. Candidates should have extensive experience in SystemVerilog and UVM, with a strong background in ASIC verification tools. The position offers a salary range of $170,000 – $196,000 based on experience.
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