Principal Engineer, PCIe Verification (AI2441)
SiMa.ai, San Jose, CA, United States
Principal Engineer, PCIe Verification (AI2441) – SiMa.ai
Job ID: AI2441
Location: San Jose, CA (full‑time, on‑site)
The Design Verification (DV) engineer at SiMa is involved in the functional verification of PCIe controller and PCIe‑phy at block, sub‑system and MLSoC levels. The role will also involve PCIe bring‑up and debug on emulator, generating required PCIe controller and phy initialization (register programming code sequence) for PCIe bring‑up in simulation, emulation and on silicon, and working on UCIe interface verification on next‑generation projects.
Responsibilities
Participate in PCIe architecture, micro‑architecture, feature discussions and reviews.
Define and develop PCIe test bench components using UVM & SystemVerilog.
Bring up and test PCIe in block and full‑chip test environments.
Develop and execute a test plan.
Execute verification of PCIe EP/RC functionality and performance measurements.
Lead code coverage reviews and closure. Develop and close SystemVerilog assertion functional coverage.
Manage debug of test and regression failures, as well as emulation failures.
Work closely with Architecture, MLSoC Hardware and MLA Software teams.
Collaborate with emulation and MLSoC Software team to bring up and debug PCIe.
Perform lab-side silicon debug of PCIe interface with software and systems teams as needed.
Required Background
BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification and silicon bring‑up/debug.
Extensive current working experience with UVM and SystemVerilog‑based verification methodology.
Experience on PCIe protocols Gen4/5.
Experience with PCIe bring‑up and debug on silicon (plus).
Past experience on UCIe protocols (plus).
Proficiency in C/C++/Python programming (plus).
Strong debug and problem‑solving skills.
Personal Attributes
Can‑do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results‑oriented. Self‑driven, thinks big and highly accountable. Good communication skills.
The annual salary for this position ranges from
$220,000
-
$296,400 . The actual annual salary paid will be based on several factors, including but not limited to skills, prior experiences, qualifications, expertise, work location, total target compensation, training, company needs, and current market demands. The annual salary range for this position is subject to change and may be adjusted in the future.
EEO Employer:
SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
Seniority Level
Mid‑Senior level
Employment Type
Full‑time
Job Function
Engineering and Information Technology
Industries
Software Development
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Job ID: AI2441
Location: San Jose, CA (full‑time, on‑site)
The Design Verification (DV) engineer at SiMa is involved in the functional verification of PCIe controller and PCIe‑phy at block, sub‑system and MLSoC levels. The role will also involve PCIe bring‑up and debug on emulator, generating required PCIe controller and phy initialization (register programming code sequence) for PCIe bring‑up in simulation, emulation and on silicon, and working on UCIe interface verification on next‑generation projects.
Responsibilities
Participate in PCIe architecture, micro‑architecture, feature discussions and reviews.
Define and develop PCIe test bench components using UVM & SystemVerilog.
Bring up and test PCIe in block and full‑chip test environments.
Develop and execute a test plan.
Execute verification of PCIe EP/RC functionality and performance measurements.
Lead code coverage reviews and closure. Develop and close SystemVerilog assertion functional coverage.
Manage debug of test and regression failures, as well as emulation failures.
Work closely with Architecture, MLSoC Hardware and MLA Software teams.
Collaborate with emulation and MLSoC Software team to bring up and debug PCIe.
Perform lab-side silicon debug of PCIe interface with software and systems teams as needed.
Required Background
BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification and silicon bring‑up/debug.
Extensive current working experience with UVM and SystemVerilog‑based verification methodology.
Experience on PCIe protocols Gen4/5.
Experience with PCIe bring‑up and debug on silicon (plus).
Past experience on UCIe protocols (plus).
Proficiency in C/C++/Python programming (plus).
Strong debug and problem‑solving skills.
Personal Attributes
Can‑do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results‑oriented. Self‑driven, thinks big and highly accountable. Good communication skills.
The annual salary for this position ranges from
$220,000
-
$296,400 . The actual annual salary paid will be based on several factors, including but not limited to skills, prior experiences, qualifications, expertise, work location, total target compensation, training, company needs, and current market demands. The annual salary range for this position is subject to change and may be adjusted in the future.
EEO Employer:
SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
Seniority Level
Mid‑Senior level
Employment Type
Full‑time
Job Function
Engineering and Information Technology
Industries
Software Development
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