Senior ASIC Design Engineer| Equity & High-Performance SoCs

A leading technology firm in Santa Clara is looking for a Senior ASIC Design Engineer. This role involves documenting and delivering verified RTL designs while collaborating with various teams. Candidates should have over 5 years of experience in hardware engineering, a strong background in VLSI, and expertise in Verilog/System Verilog. The position offers competitive salaries ranging from $136,000 to $218,500 and additional equity opportunities. Join a diverse and innovative company driving advances in technology.
#J-18808-Ljbffr