Fullchip Floorplan Design Engineer
Intel, Fort Collins, CO, United States
Job Details
Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
The Role
We are looking for a talented and motivated Physical Design Floorplanning Engineer to join our team. In this role key responsibilities are:
Top‑down SoC floorplan activities such as best IP placement for latency/area in collaboration with architects, partitioning, PG grid creation, pin‑cutting, bump‑planning by working with package/platform. Estimate die‑area and define optimal physical dimensions for SoC by including product costs such as die‑per‑reticle, technology selection/metal stack and reuse from different product families.
Drive execution and supervise progress of smaller blocks or sub‑systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule. Plan short and long‑term work schedule, understanding dependencies between different domains such as top place, block place, and route.
Responsibilities
Collaborate with stakeholders such as the clock design team to deliver physical block‑level floorplans for APR and with the power delivery team on trade‑offs for metal allocation for signal and power.
Experienced in industry‑standard tools.
Help drive methodologies, tools and best practices to streamline floorplan physical design work to achieve best‑in‑class on‑schedule delivery.
Minimum Qualifications
Bachelor in Electrical/Electronics/Computer Engineering with 4+ years of relevant experience or Master’s degree in Electrical/Electronics/Computer Engineering with 3+ years of relevant experience.
3+ years of experience using industry‑standard EDA tools for floorplanning and APR.
1+ year of experience with Synopsys Fusion Compiler.
4+ years of experience with TCL, Python or Perl programming.
2+ years of experience with Calibre or ICV verification.
Preferred Qualifications
Good knowledge of all aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and macro placement.
Familiar with hierarchical design approach, top‑down design, handling MIB (multiple instantiation blocks), routing and physical convergence.
Deep knowledge of SoC floorplan requirements such as multiple voltage and clock domains, level shifters, thermal management, die‑to‑die interconnects, and package interactions.
Expertise with floorplanning tools – IC\_2/FC, place and route flows, and physical design verification flows.
Experience with large subsystem designs (20M gates) with frequencies in excess of 2 GHz.
Good automation skills/focus with coding familiarity in TCL/Perl/Python.
Excellent communication and teamwork skills.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Texas, Austin
Additional Locations
US, California, Folsom; US, California, Santa Clara; US, Colorado, Fort Collins; US, Massachusetts, Beaver Brook; US, Oregon, Hillsboro
Business Group
At the Data Center Group (DCG), we’re committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload‑driven leadership products and close collaboration with our partners.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
The Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Salary Range
Annual salary range for jobs which could be performed in the US: $141,910.00 – $269,100.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
Work Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.
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Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
The Role
We are looking for a talented and motivated Physical Design Floorplanning Engineer to join our team. In this role key responsibilities are:
Top‑down SoC floorplan activities such as best IP placement for latency/area in collaboration with architects, partitioning, PG grid creation, pin‑cutting, bump‑planning by working with package/platform. Estimate die‑area and define optimal physical dimensions for SoC by including product costs such as die‑per‑reticle, technology selection/metal stack and reuse from different product families.
Drive execution and supervise progress of smaller blocks or sub‑systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule. Plan short and long‑term work schedule, understanding dependencies between different domains such as top place, block place, and route.
Responsibilities
Collaborate with stakeholders such as the clock design team to deliver physical block‑level floorplans for APR and with the power delivery team on trade‑offs for metal allocation for signal and power.
Experienced in industry‑standard tools.
Help drive methodologies, tools and best practices to streamline floorplan physical design work to achieve best‑in‑class on‑schedule delivery.
Minimum Qualifications
Bachelor in Electrical/Electronics/Computer Engineering with 4+ years of relevant experience or Master’s degree in Electrical/Electronics/Computer Engineering with 3+ years of relevant experience.
3+ years of experience using industry‑standard EDA tools for floorplanning and APR.
1+ year of experience with Synopsys Fusion Compiler.
4+ years of experience with TCL, Python or Perl programming.
2+ years of experience with Calibre or ICV verification.
Preferred Qualifications
Good knowledge of all aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and macro placement.
Familiar with hierarchical design approach, top‑down design, handling MIB (multiple instantiation blocks), routing and physical convergence.
Deep knowledge of SoC floorplan requirements such as multiple voltage and clock domains, level shifters, thermal management, die‑to‑die interconnects, and package interactions.
Expertise with floorplanning tools – IC\_2/FC, place and route flows, and physical design verification flows.
Experience with large subsystem designs (20M gates) with frequencies in excess of 2 GHz.
Good automation skills/focus with coding familiarity in TCL/Perl/Python.
Excellent communication and teamwork skills.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Texas, Austin
Additional Locations
US, California, Folsom; US, California, Santa Clara; US, Colorado, Fort Collins; US, Massachusetts, Beaver Brook; US, Oregon, Hillsboro
Business Group
At the Data Center Group (DCG), we’re committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload‑driven leadership products and close collaboration with our partners.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
The Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Salary Range
Annual salary range for jobs which could be performed in the US: $141,910.00 – $269,100.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
Work Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.
#J-18808-Ljbffr