Senior CPU RTL Design Engineer - Power & Performance

A global technology leader is seeking a CPU Logic Design Engineer in Phoenix, Arizona, to develop and optimize logic for cutting-edge processors. The role involves writing RTL code, ensuring design integrity, and collaborating with SoC customers. Candidates should possess at least 7 years of relevant experience with a strong foundation in RTL design using Verilog. This position offers competitive compensation and the flexibility of a hybrid work model.
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