
Senior ASIC Design Automation Architect
Ayar Labs, San Jose, CA, United States
A leading optical I/O technology firm in San Jose is seeking a Chip Design Automation Engineer. You will lead design automation and methodologies for complex ASICs, focusing on flow architecture, tool integration, and optimization. Ideal candidates have 5+ years in Chip Design Automation with strong scripting abilities and a solid understanding of ASIC design flows. This position offers a competitive salary and the opportunity to work in a dynamic, innovative environment.
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