Macro Analog Design Engineer
Rapidus Corporation US, Albany, NY, United States
Position Summary
This position focuses on macro and custom layout design for evaluation macros, memory, logic, and analog/mixed-signal functional blocks in advanced semiconductor process and device development.
Through layout optimization considering PPA (Performance, Power, Area), reliability, manufacturability (DFM), and yield, the engineer contributes to the validation and advancement of process and device technologies.
The engineer will work closely with circuit designers, process/device teams, and PDK teams, and will play a key role throughout the development phases from early design through volume ramp.
Key Responsibilities
Macro Layout (Primary Responsibility)
Macro/custom layout design for memory, logic, and analog/mixed-signal functional blocks
Layout variation design intended for device characterization and process validation
Layout optimization considering DRC/LVS/DFM/DFY, EMIR, and reliability
Layout design and revision control for test chips (TEGs) and evaluation macros
Support correlation analysis between silicon results (electrical characteristics, reliability, yield) and layout conditions
Cross-Functional Collaboration
Collaborate with circuit designers to define layout constraints reflecting circuit intent
Work with process and device development teams to define evaluation conditions and viewpoints
Provide feedback to PDKs, including design rules and layout guidelines
Contribute to circuit design for memory, logic, or analog blocks
Perform circuit simulation and variability analysis using SPICE or equivalent tools
Take ownership of post-layout circuit verification
Propose optimization by integrating circuit conditions and physical implementation conditions
Lead development of evaluation macros spanning both circuit and layout domains
Required Qualifications
Bachelor’s degree or higher in Semiconductor Engineering, Electrical Engineering, Physics, or a related field
3+ years of hands-on experience in macro/custom layout design
Experience with DRC/LVS-based verification flows
Fundamental knowledge of advanced process design rules and manufacturing constraints
Basic understanding of circuit operation
Preferred Qualifications
Experience with advanced technology nodes (7nm or below, FinFET/GAA, etc.)
Experience in memory or analog/mixed-signal circuit design
Cross-functional experience with process and/or device development teams
Ability to communicate technical topics effectively in English
Desired Attributes
Strong technical curiosity and proactive approach to problem solving
Ability to collaborate effectively with cross-functional teams
Flexibility to work in fast-paced and uncertain advanced R&D environments
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This position focuses on macro and custom layout design for evaluation macros, memory, logic, and analog/mixed-signal functional blocks in advanced semiconductor process and device development.
Through layout optimization considering PPA (Performance, Power, Area), reliability, manufacturability (DFM), and yield, the engineer contributes to the validation and advancement of process and device technologies.
The engineer will work closely with circuit designers, process/device teams, and PDK teams, and will play a key role throughout the development phases from early design through volume ramp.
Key Responsibilities
Macro Layout (Primary Responsibility)
Macro/custom layout design for memory, logic, and analog/mixed-signal functional blocks
Layout variation design intended for device characterization and process validation
Layout optimization considering DRC/LVS/DFM/DFY, EMIR, and reliability
Layout design and revision control for test chips (TEGs) and evaluation macros
Support correlation analysis between silicon results (electrical characteristics, reliability, yield) and layout conditions
Cross-Functional Collaboration
Collaborate with circuit designers to define layout constraints reflecting circuit intent
Work with process and device development teams to define evaluation conditions and viewpoints
Provide feedback to PDKs, including design rules and layout guidelines
Contribute to circuit design for memory, logic, or analog blocks
Perform circuit simulation and variability analysis using SPICE or equivalent tools
Take ownership of post-layout circuit verification
Propose optimization by integrating circuit conditions and physical implementation conditions
Lead development of evaluation macros spanning both circuit and layout domains
Required Qualifications
Bachelor’s degree or higher in Semiconductor Engineering, Electrical Engineering, Physics, or a related field
3+ years of hands-on experience in macro/custom layout design
Experience with DRC/LVS-based verification flows
Fundamental knowledge of advanced process design rules and manufacturing constraints
Basic understanding of circuit operation
Preferred Qualifications
Experience with advanced technology nodes (7nm or below, FinFET/GAA, etc.)
Experience in memory or analog/mixed-signal circuit design
Cross-functional experience with process and/or device development teams
Ability to communicate technical topics effectively in English
Desired Attributes
Strong technical curiosity and proactive approach to problem solving
Ability to collaborate effectively with cross-functional teams
Flexibility to work in fast-paced and uncertain advanced R&D environments
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