Sr Design Verification Engineer - RISC-V
ManpowerGroup Global, Inc., Granite Heights, WI, United States
Design Verification Engineer - Senior Level (15+ years)
Duration: 10-12+ Months Contract
Locations: Remote (California, Oregon, Washington)
Pay Range: $80-$85/hr on W2, 40 Hrs
Description
The top 6 skills are must skills and the rest are preferred. Basic DV skills such as System Verilog/UVM, assertions, coverage, random constraints, etc. are also required.
RISC‑V architecture knowledge and verification experience
VC Formal DPV App (Datapath Verification) which checks the RTL against C/C++ models for arithmetic conformance
L3 cache coherent system with AXI and CHI interfaces
C/C++
Synopsys tools, VCS, VC Formal
Python based simulation flow
Wide Vector Unit and a Matmul Unit
Formal verification
SOC System integration required, e.g., booting Linux OS
GLS (Gate Level Simulation)
Low Power experience (CPF/UPF)
#J-18808-Ljbffr
Duration: 10-12+ Months Contract
Locations: Remote (California, Oregon, Washington)
Pay Range: $80-$85/hr on W2, 40 Hrs
Description
The top 6 skills are must skills and the rest are preferred. Basic DV skills such as System Verilog/UVM, assertions, coverage, random constraints, etc. are also required.
RISC‑V architecture knowledge and verification experience
VC Formal DPV App (Datapath Verification) which checks the RTL against C/C++ models for arithmetic conformance
L3 cache coherent system with AXI and CHI interfaces
C/C++
Synopsys tools, VCS, VC Formal
Python based simulation flow
Wide Vector Unit and a Matmul Unit
Formal verification
SOC System integration required, e.g., booting Linux OS
GLS (Gate Level Simulation)
Low Power experience (CPF/UPF)
#J-18808-Ljbffr