Engineer / Senior Engineer, Physical Design (ASIC Place & Route) (San Jose, CA)
TSMC - Taiwan Semiconductor Manufacturing Company Limited, San Jose, CA, United States
Overview As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff. You will be reporting to Senior Manager at San Jose Center and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office.
Responsibilities
Complete entire physical implementation of the block level and tapeout production chip
Block level floorplan with the ability to analyze the quality of the floorplan
Customized Clock tree structure and Place & Route
Implement ECOs for timing closure
Signal EM/Noise and PowerIR/EM analysis and fix
DRC/LVS/ERC/ANTENNA analysis and clean up
Physical verification sign off
Minimum Qualifications
Master’s degree in Electrical/Computer Science Engineering with 3+ years of industry experience
Netlist (or RTL)-GDS physical implementation experience
In depth knowledge of major EDA tools/design flows
Experience with TSMC N16 or below technology
Experience in block level implementation or chip integration and signoff
Experience in Perl/TCL language programming
Ability to work regularly at a Customer site in the South Bay Area.
Preferred Qualifications
TSMC N5 and below technology
Low-power implementation methodology
Advanced timing signoff methodology
Able to independently complete Netlist-GDS P&R, signoff task
Proven record in multi-million gate design production tapeouts
Diversity statement
TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.
TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at g_accommodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.
Pay Transparency / Benefits statement
At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $110,000 and $160,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC’s total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.
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Responsibilities
Complete entire physical implementation of the block level and tapeout production chip
Block level floorplan with the ability to analyze the quality of the floorplan
Customized Clock tree structure and Place & Route
Implement ECOs for timing closure
Signal EM/Noise and PowerIR/EM analysis and fix
DRC/LVS/ERC/ANTENNA analysis and clean up
Physical verification sign off
Minimum Qualifications
Master’s degree in Electrical/Computer Science Engineering with 3+ years of industry experience
Netlist (or RTL)-GDS physical implementation experience
In depth knowledge of major EDA tools/design flows
Experience with TSMC N16 or below technology
Experience in block level implementation or chip integration and signoff
Experience in Perl/TCL language programming
Ability to work regularly at a Customer site in the South Bay Area.
Preferred Qualifications
TSMC N5 and below technology
Low-power implementation methodology
Advanced timing signoff methodology
Able to independently complete Netlist-GDS P&R, signoff task
Proven record in multi-million gate design production tapeouts
Diversity statement
TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.
TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at g_accommodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.
Pay Transparency / Benefits statement
At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $110,000 and $160,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC’s total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.
#J-18808-Ljbffr