RTL Design Engineer: Multimedia & ML Accelerators

A leading technology company is seeking an experienced RTL Design Engineer for their location in Mountain View, California. The role involves designing RTL digital logic and verifying its performance using SystemVerilog. Candidates should have extensive experience with FPGA/ASIC design and proficiency in scripting languages such as Perl or Python. The position offers a comprehensive salary package between $163,000 and $237,000 along with bonuses and equity. Join a team pioneering custom silicon solutions for innovative products.
#J-18808-Ljbffr