Silicon Photonics Design & Integration Engineer
cspeed inc, Palo Alto, CA, United States
Cspeed IO is a stealth start up backed by Sutter Hills Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber‑optic technologies that overcome the limitations of existing optics solutions and architectures.
Responsibilities
Integrate photonic devices and circuit blocks from multiple contributors into complete PIC designs, maintaining performance, layout integrity, and manufacturability throughout.
Drive silicon photonics tape‑outs from design freeze through foundry submission—ensuring compliance with PDK requirements, foundry design rules, and DRC/LVS sign‑off.
Work with photonic designers to drive layout implementation, verification, and tape‑out readiness; identify and resolve integration conflicts early in the design cycle.
Serve as a technical interface with silicon photonics foundry partners to resolve design rule, integration, and manufacturability issues.
Collaborate closely with electronics interface (EI), system architecture, and packaging teams to ensure photonic circuits integrate correctly with electrical interfaces, system requirements, and packaging constraints.
Qualifications
Strong understanding of silicon photonic device physics and operation, with practical experience designing or integrating silicon photonic devices or circuits.
5 or more years of relevant industry experience in silicon photonics design, integration, or tape‑out.
Familiarity with silicon photonics process technology, layer stacks, and fabrication constraints as they relate to integration and layout decisions.
Experience with PDK‑based design flows and photonic layout tools such as Cadence, KLayout, Luceda IPKISS, or equivalent.
Demonstrated experience supporting PIC layout integration and tape‑out activities, including DRC verification and foundry submission.
Strong cross‑functional ownership mindset—able to proactively drive integration work to completion and resolve conflicts across design, EI, systems, and packaging teams.
Experience working directly with silicon photonics foundries on integration and manufacturability issues.
Experience integrating complex photonic circuits or multi‑function subsystems.
Hands‑on experience with photonic device characterization or validation.
Experience collaborating across photonics, electronics interface, system, and packaging teams on co‑design or integration challenges.
Education
Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline. Candidates with relevant industry experience and a demonstrated track record of PIC integration and tape‑out ownership may be considered without a Ph.D.
#J-18808-Ljbffr
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber‑optic technologies that overcome the limitations of existing optics solutions and architectures.
Responsibilities
Integrate photonic devices and circuit blocks from multiple contributors into complete PIC designs, maintaining performance, layout integrity, and manufacturability throughout.
Drive silicon photonics tape‑outs from design freeze through foundry submission—ensuring compliance with PDK requirements, foundry design rules, and DRC/LVS sign‑off.
Work with photonic designers to drive layout implementation, verification, and tape‑out readiness; identify and resolve integration conflicts early in the design cycle.
Serve as a technical interface with silicon photonics foundry partners to resolve design rule, integration, and manufacturability issues.
Collaborate closely with electronics interface (EI), system architecture, and packaging teams to ensure photonic circuits integrate correctly with electrical interfaces, system requirements, and packaging constraints.
Qualifications
Strong understanding of silicon photonic device physics and operation, with practical experience designing or integrating silicon photonic devices or circuits.
5 or more years of relevant industry experience in silicon photonics design, integration, or tape‑out.
Familiarity with silicon photonics process technology, layer stacks, and fabrication constraints as they relate to integration and layout decisions.
Experience with PDK‑based design flows and photonic layout tools such as Cadence, KLayout, Luceda IPKISS, or equivalent.
Demonstrated experience supporting PIC layout integration and tape‑out activities, including DRC verification and foundry submission.
Strong cross‑functional ownership mindset—able to proactively drive integration work to completion and resolve conflicts across design, EI, systems, and packaging teams.
Experience working directly with silicon photonics foundries on integration and manufacturability issues.
Experience integrating complex photonic circuits or multi‑function subsystems.
Hands‑on experience with photonic device characterization or validation.
Experience collaborating across photonics, electronics interface, system, and packaging teams on co‑design or integration challenges.
Education
Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline. Candidates with relevant industry experience and a demonstrated track record of PIC integration and tape‑out ownership may be considered without a Ph.D.
#J-18808-Ljbffr