Layout Design Engineer
MRL Consulting Group | Global Niche Technology Recruitment, San Francisco, CA, United States
The Opportunity We’re partnering with a well-funded, venture-backed semiconductor start-up in the Bay Area building next-generation high-speed connectivity and optical interconnect solutions .
They are looking for a hands-on RFIC / MMIC Layout Engineer to take ownership of layout for cutting-edge designs across mmWave, high-speed analog, and optical interface ICs .
The Opportunity
This is a chance to join a small, elite engineering team where layout is treated as a critical part of performance—not a back-end function. You’ll work directly with RF and analog designers to push the limits of bandwidth, noise, and signal integrity in advanced nodes and compound semiconductor processes.
What You’ll Be Doing Own full-custom layout of RF / mmWave / high-speed analog blocks (e.g. amplifiers, TIAs, drivers)
Implement EM-aware layouts including transmission lines, matching networks, shielding, and isolation
Work closely with designers on parasitic extraction and performance closure
Contribute to first silicon success in a fast-paced tape-out environment
What We’re Looking For 5+ years in RFIC / MMIC layout
Strong experience with Cadence Virtuoso (or similar)
Solid understanding of RF parasitics, coupling, and high-frequency effects
Background in one or more:
GaAs / GaN / InP
Experience supporting tape-outs at >20 GHz (ideally much higher)
Nice to Have Exposure to optical / photonics ICs (TIA, drivers)
Experience with EM tools (HFSS, Momentum, EMX)
Background in coherent optics or high-speed SerDes
Competitive base + meaningful equity
Targeting $150k – $220k base (flexible for top candidates)
Strong upside in a high-growth environment
#J-18808-Ljbffr
They are looking for a hands-on RFIC / MMIC Layout Engineer to take ownership of layout for cutting-edge designs across mmWave, high-speed analog, and optical interface ICs .
The Opportunity
This is a chance to join a small, elite engineering team where layout is treated as a critical part of performance—not a back-end function. You’ll work directly with RF and analog designers to push the limits of bandwidth, noise, and signal integrity in advanced nodes and compound semiconductor processes.
What You’ll Be Doing Own full-custom layout of RF / mmWave / high-speed analog blocks (e.g. amplifiers, TIAs, drivers)
Implement EM-aware layouts including transmission lines, matching networks, shielding, and isolation
Work closely with designers on parasitic extraction and performance closure
Contribute to first silicon success in a fast-paced tape-out environment
What We’re Looking For 5+ years in RFIC / MMIC layout
Strong experience with Cadence Virtuoso (or similar)
Solid understanding of RF parasitics, coupling, and high-frequency effects
Background in one or more:
GaAs / GaN / InP
Experience supporting tape-outs at >20 GHz (ideally much higher)
Nice to Have Exposure to optical / photonics ICs (TIA, drivers)
Experience with EM tools (HFSS, Momentum, EMX)
Background in coherent optics or high-speed SerDes
Competitive base + meaningful equity
Targeting $150k – $220k base (flexible for top candidates)
Strong upside in a high-growth environment
#J-18808-Ljbffr